Optimizing the Implementation of SEC–DAEC Codes in FPGAs - 2016


Single error correction and double-adjacent error correction (SEC-DAEC) codes are a kind of error correction codes (ECCs) capable of correcting single and double-adjacent errors. They are useful in applications where multiple adjacent errors may occur, like house or avionics. ECC encoders and decoders have a regular structure that produces it easier to accommodate them into field-programmable gate arrays (FPGAs). This temporary proposes ways to optimize the decoder of SEC-DAEC codes when implemented in an FPGA, reducing the resource utilization in comparison with the traditional implementations.

Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here

PROJECT TITLE :Optimizing Performance of Co-Existing Underlay Secondary Networks - 2018ABSTRACT:In this Project, we have a tendency to analyze total throughput and (asymptotic) total ergodic rate performance of 2 co-existing downlink
PROJECT TITLE :Optimizing Internet Transit Routing for Content Delivery Networks - 2018ABSTRACT:Content delivery networks (CDNs) maintain multiple transit routes from content distribution servers to eyeball ISP networks that
PROJECT TITLE :A Ternary Unification Framework for Optimizing TCAM-Based Packet Classification Systems - 2018ABSTRACT:Packet classification is that the key mechanism for enabling many networking and security services. Ternary
PROJECT TITLE :Optimizing for Tail Sojourn Times of Cloud Clusters - 2018ABSTRACT:A standard pitfall when hosting applications in these days's cloud environments is that virtual servers often experience varying execution speeds
PROJECT TITLE :Optimizing Power-Accuracy trade-off in Approximate Adders - 2018ABSTRACT:Approximate circuit design has gained significance in recent years targeting applications like media processing where full accuracy isn't

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry