PROJECT TITLE :
Optimizing the Implementation of SEC–DAEC Codes in FPGAs - 2016
Single error correction and double-adjacent error correction (SEC-DAEC) codes are a kind of error correction codes (ECCs) capable of correcting single and double-adjacent errors. They are useful in applications where multiple adjacent errors may occur, like house or avionics. ECC encoders and decoders have a regular structure that produces it easier to accommodate them into field-programmable gate arrays (FPGAs). This temporary proposes ways to optimize the decoder of SEC-DAEC codes when implemented in an FPGA, reducing the resource utilization in comparison with the traditional implementations.
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