Optimizing the Implementation of SEC–DAEC Codes in FPGAs - 2016 PROJECT TITLE : Optimizing the Implementation of SEC–DAEC Codes in FPGAs - 2016 ABSTRACT: Single error correction and double-adjacent error correction (SEC-DAEC) codes are a kind of error correction codes (ECCs) capable of correcting single and double-adjacent errors. They are useful in applications where multiple adjacent errors may occur, like house or avionics. ECC encoders and decoders have a regular structure that produces it easier to accommodate them into field-programmable gate arrays (FPGAs). This temporary proposes ways to optimize the decoder of SEC-DAEC codes when implemented in an FPGA, reducing the resource utilization in comparison with the traditional implementations. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Field Programmable Gate Arrays Decoding Error Correction Codes Error Correction Codes (Eccs) Field-Programm-Able Gate Arrays (FPGAS) Lookup Tables (LUTS) Single Error Correction And Double-Adjacent Error Correction (Sec???Daec) A Multimode Area-Efficient SCL Polar Decoder - 2016 A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction - 2016