A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction - 2016


Single error correction and double-adjacent error correction (SEC-DAEC) codes are a type of error correction codes (ECCs) capable of correcting single and double-adjacent errors. They're useful in applications where multiple adjacent errors might occur, such as space or avionics. ECC encoders and decoders have a regular structure that produces it easier to accommodate them into field-programmable gate arrays (FPGAs). This brief proposes strategies to optimize the decoder of SEC-DAEC codes when implemented in an FPGA, reducing the resource utilization compared with the traditional implementations.

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