A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction - 2016 PROJECT TITLE : A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction - 2016 ABSTRACT: Single error correction and double-adjacent error correction (SEC-DAEC) codes are a type of error correction codes (ECCs) capable of correcting single and double-adjacent errors. They're useful in applications where multiple adjacent errors might occur, such as space or avionics. ECC encoders and decoders have a regular structure that produces it easier to accommodate them into field-programmable gate arrays (FPGAs). This brief proposes strategies to optimize the decoder of SEC-DAEC codes when implemented in an FPGA, reducing the resource utilization compared with the traditional implementations. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Error Statistics Cache Storage Error Correction Radiation Hardening (Electronics) Interleaved Codes Optimizing the Implementation of SEC–DAEC Codes in FPGAs - 2016 High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m) - 2016
