A 520k (18 900, 17 010) Array Dispersion LDPC Decoder Architectures for NAND-Flash Memory - 2016


Though Latin square may be a well-known algorithm to construct low-density parity-check (LDPC) codes for satisfying long code length, high code-rate, sensible correcting capability, and low error floor, it has a drawback of huge sub matrix that the hardware implementation can be suffered from giant barrel shifter and worse routing congestion in fitting NAND flash applications. In this paper, a top-down style methodology, which not solely goes through code construction and optimization, but additionally hardware implementation to meet all the critical necessities, is presented. A 2-step array dispersion algorithm is proposed to construct long LDPC codes with a tiny sub matrix size. Then, the constructed LDPC code is optimized by masking matrix to obtain higher bit-error rate (BER) performance and lower error floor. In addition, our LDPC codes have a diagonal-like structure in the parity-check matrix resulting in a proposed hybrid storage architecture, that has the advantages of better area efficiency and massive enough data bandwidth for prime decoding throughput. To be adopted for NAND flash applications, an (eighteen 900, 17 010) LDPC code with a code-rate of 0.9 and sub matrix size of sixty three is made and the sector-programmable gate array simulations show that the error floor is successfully suppressed right down to BER of 10 -12. The proposed design of this paper analysis the logic size, space and power consumption using Xilinx fourteen.2.

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