Hybrid LUT/Multiplexer FPGA Logic Architectures - 2016

PROJECT TITLE :

Hybrid LUT/Multiplexer FPGA Logic Architectures - 2016

ABSTRACT:

Hybrid configurable logic block architectures for field-programmable gate arrays that contain a combination of lookup tables and hardened multiplexers are evaluated toward the goal of upper logic density and area reduction. Multiple hybrid configurable logic block architectures, both nonfracturable and fracturable with varying MUX:LUT logic part ratios are evaluated across two benchmark suites (VTR and CHStone) employing a custom tool flow consisting of LegUp-HLS, Odin-II front-finish synthesis, ABC logic synthesis and technology mapping, and VPR for packing, placement, routing, and design exploration. Technology mapping optimizations that target the proposed architectures also are implemented inside ABC. Experimentally, we tend to show that for nonfracturable architectures, without any mapper optimizations, we have a tendency to naturally save up to ~8p.c space postplace and route; each accounting for advanced logic block and routing space whereas maintaining mapping depth. With design-aware technology mapper optimizations in ABC, further space is saved, post-place-and-route. For fracturable architectures, experiments show that only marginal gains are seen once place-and-route up to ~a pair ofp.c. For both nonfracturable and fracturable architectures, we have a tendency to see minimal impact on timing performance for the architectures with best space-efficiency.

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