Technology optimized fixed-point bit-parallel multiplier for LUT based FPGAs - 2015


Modern day field programmable gate arrays (FPGA) have look-up tables (LUT) as inherent basic logic components. With FPGAs fast moving from prototype designing to low and medium volume productions, there is an increased want for economical utilization of these FPGA primitives. Unfortunately majority of the work involved with FPGA implementations focus only on the technology independent (architectural) optimizations which will be done at the top level of the logic synthesis method. Once a design has been modified architecturally, its behavioral description is fed to the synthesizer that drives the logic synthesis process as per the specified value function. Any technology dependent optimization done by the synthesizer is thus hidden from the designer. In this project we tend to contemplate the technology dependent optimization of the fixed-point bit-parallel multiplier on LUT based mostly FPGAs. We have a tendency to perform technology dependent optimizations previous to the design entry phase and then use instantiation based mostly coding designs to confirm that the optimizations stay preserved throughout the synthesis method. We tend to have compared our implementation results against various mounted-point multipliers reported in [twenty eight]. Our implementations show substantial improvement in terms of resources used, crucial path delays and dynamic power dissipation. An important feature of technology dependent optimizations is that it ends up in a simultaneous improvement of all the performance parameters. This is in contrast to the technology independent optimizations where there is always an application-driven trade-off between different performance parameters.

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