Technology optimized fixed-point bit-parallel multiplier for LUT based FPGAs - 2015

PROJECT TITLE:

Technology optimized fixed-point bit-parallel multiplier for LUT based FPGAs - 2015

ABSTRACT:

Look-up tables are inherent simple logic components of modern day field programmable gate arrays (FPGA) (LUT). There is an increased need for these FPGA primitives to be used commercially, with FPGAs moving rapidly from prototype design to low to medium volume output. Unfortunately, much of the work involved in the implementation of FPGA focuses only on (architectural) technology-independent optimizations that are carried out at the top level of the logic synthesis process. After a design has been updated architecturally, its behavioral definition is fed to the synthesizer that drives the logic synthesis process as per the defined value function. Thus the designer is hidden from any optimization performed by the synthesizer that depends on technology. In this project, we prefer to consider technology-dependent optimization of the fixed-point bit-parallel multiplier based mostly on LUT based FPGAs. We prefer to perform technology-dependent optimizations before the design entry process and then use mostly instantiation-based coding designs to confirm that the optimizations remain preserved in the synthesis method. We prefer to equate our implementation results with the multiple multipliers of mounted points recorded in[twenty-eight]. Our implementations show significant progress in terms of resources used, critical route delays and complex power dissipation. An significant feature of technology-dependent optimizations is that all parameters of output end up being changed simultaneously. This is where an application-driven trade-off between various performance parameters is always present, unlike technology-independent optimizations.

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