Analysis of ternary multiplier using booth encoding technique - 2015
This project introduces a new approach to multiplication of ternary numbers. The whole multiplication relies on the economical Booth Encoding technique that multiplies each positive with negative ternary numbers. Verilog HDL has been used to implement the ternary multipliers of 3bit, 8bit and 12bit. The HDL design is predicated on the Finite State Machine (FSM) and multiplexing techniques. The planning is simulated using ModelSim SE vi.5 and synthesized using Xilinx ISE Style Suite fourteen.one. The results obtained from the proposed style in terms of delay, power and space are compared with the traditional multiplier design.
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