FPGA based partial reconfigurable fir filter design - 2014


This project proposes partial reconfigurable FIR filter design using systolic Distributed Arithmetic (DA) architecture optimized for FPGAs. To implement computationally efficient, low power, high speed Finite Impulse Response (FIR) filter a two dimensional absolutely pipelined structure is employed. To scale back the partial reconfiguration time a replacement design for the Look-Up Table (LUT) in distributed arithmetic is proposed. The FIR filter is dynamically reconfigured to understand low pass and high pass filter characteristics by changing the filter coefficients in the partial reconfiguration module. The look is implemented using XUP Virtex five LX110T FPGA kit. The FIR filter design shows improvement in configuration time and potency.

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