An Efficient VLSI Architecture of a Reconfigurable Pulse Shaping FIR Interpolation Filter for Multistandard DUC - 2014
This temporary proposes a 2-step optimization technique for designing a reconfigurable VLSI design of an interpolation filter for multistandard digital up converter (DUC) to reduce the facility and area consumption. The proposed technique initially reduces the number of multiplications per input sample and additions per input sample by 83p.c in comparison with individual implementation of each customary's filter while coming up with a root-raised-cosine finite-impulse response filter for multistandard DUC for 3 completely different standards. In the following step, a a pair of-bit binary common subexpression (BCS)-based BCS elimination algorithm has been proposed to style an efficient constant multiplier, which is the basic part of any filter. This technique has succeeded in reducing the area and power usage by forty one% and thirty eight%, respectively, together with thirty sixpercent improvement in operating frequency over a three-bit BCS-based technique reported earlier, and can be thought-about a lot of applicable for coming up with the multistandard DUC.
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