Low Voltage and Low Power 64-bit Hybrid Adder Design Based on Radix-4 Prefix Tree Structure - 2014


A 64-bit hybrid adder style is proposed by using both radix-four prefix tree structure and carry select adder for low voltage and low power applications. In order to optimize the features of this adder, some design problems are involved together with optimal layout for CMOS group generate/propagate circuit to scale back area, design of carry bypass adder (CBA) without conflict to boost speed, carry select adder (CSA) style with speed and space efficiency, and therefore on. Based on TSMC ninety nm CMOS mixed signal process technology at 1V supply voltage, the experimental results reveal that the proposed 64-bit hybrid adder is superior to different referenced adders, and has 203 ps delay time, nine.58 mw average power, and ninety six×seventy six µm2 area.

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