Aging Aware Reliable Multiplier Design With Adaptive Hold Logic - 2014
Digital multipliers are among the foremost essential arithmetic useful units. The overall performance of those systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability result happens when a pMOS transistor is beneath negative bias (Vgs = -Vdd), increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Each effects degrade transistor speed, and in the long run, the system could fail thanks to timing violations. Therefore, it is vital to design reliable high-performance multipliers. In this project, we tend to propose an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is ready to supply higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that's because of the aging impact. Moreover, the proposed design will be applied to a columnor row-bypassing multiplier. The experimental results show that our proposed architecture with sixteen × sixteen and thirty two × thirty two column-bypassing multipliers can attain up to sixty two.88percent and seventy six.twenty eightp.c performance improvement, respectively, compared with sixteen×sixteen and thirty two×thirty two fastened-latency column-bypassing multipliers. Furthermore, our proposed design with sixteen × 16 and thirty two × 32 row-bypassing multipliers will achieve up to eighty.seventeenpercent and 69.forty% performance improvement as compared with sixteen×sixteen and thirty two × thirty two fastened-latency row-bypassing multipliers.
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