Area Delay Power Efficient Carry Select Adder - 2014

PROJECT TITLE:

Area Delay Power Efficient Carry Select Adder - 2014

ABSTRACT:

In this brief, the logic operations concerned in conventional carry select adder (CSLA) and binary to excess-one converter (BEC)-based CSLA are analyzed to study the data dependence and to spot redundant logic operations. We have eliminated all the redundant logic operations present in the conventional CSLA and proposed a replacement logic formulation for CSLA. Within the proposed theme, the carry select (CS) operation is scheduled before the calculation of final-add, which is totally different from the conventional approach. Bit patterns of two anticipating carry words (corresponding tocin=zero and one) and mounted cin bits are used for logic optimization of CS and generation units. An efficient CSLA style is obtained using optimized logic units. The proposed CSLA design involves significantly less area and delay than the recently proposed BEC-based CSLA. Due to the tiny carry-output delay, the proposed CSLA style is a sensible candidate for square-root (SQRT) CSLA. A theoretical estimate shows that the proposed SQRT-CSLA involves nearly thirty fivep.c less area–delay–product (ADP) than the BEC-based SQRT-CSLA, that is best among the prevailing SQRT-CSLA designs, on average, for different bit-widths. The application-specified integrated circuit (ASIC) synthesis result shows that the BEC-primarily based SQRT-CSLA style involves forty eight% more ADP and consumes 50p.c additional energy than the proposed SQRT-CSLA, on average, for various bit-widths.

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