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451 |
Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing - 2015 |
Abstract
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452 |
Digtial to time converter using SET - 2015 |
Abstract
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453 |
Design of high speed ternary full adder and threeinput XOR circuits using CNTFETs - 2015 |
Abstract
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454 |
Design Method of Single-Flux-Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates - 2015 |
Abstract
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|
455 |
Design and simulation of single layered Logic Generator Block using Quantum Dot Cellular Automata - 2015 |
Abstract
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|
456 |
Design and Performance Evaluation of A Low Transistor Ternary CNTFET SRAM Cell - 2015 |
Abstract
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|
457 |
A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process - 2015 |
Abstract
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458 |
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist - 2015 |
Abstract
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|
459 |
A High Speed 256-Bit Carry Look Ahead Adder Design Using 22nm Strained Silicon Technology - 2015 |
Abstract
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|
460 |
A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable Active Inductor for 10-Gb/s I/O Links - 2015 |
Abstract
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|
461 |
A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique - 2015 |
Abstract
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|
462 |
An All-Digital Scalable and Reconfigurable Wide-Input Range Stochastic ADC Using Only Standard Cells - 2015 |
Abstract
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|
463 |
Read Performance The Newest Barrier in Scaled STT-RAM - 2015 |
Abstract
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|
464 |
On the Nonvolatile Performance of Flip-FlopSRAM Cells With a Single MTJ - 2015 |
Abstract
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465 |
High-Performance and High-Yield 5 nm Underlapped FinFET SRAM Design using P-type Access Transistors - 2015 |
Abstract
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|
466 |
High-Frequency CMOS Active Inductor Design Methodology and Noise Analysis - 2015 |
Abstract
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|
467 |
Efficient Static D-Latch Standard Cell Characterization Using a Novel Setup Time Model - 2015 |
Abstract
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|
468 |
A CMOS PWM Transceiver Using Self-Referenced Edge Detection - 2015 |
Abstract
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|
469 |
Area Delay Power Efficient Carry Select Adder - 2014 |
Abstract
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|
470 |
On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays - 2014 |
Abstract
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|
471 |
Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code - 2014 |
Abstract
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|
472 |
A Method to Extend Orthogonal Latin Square Codes - 2014 |
Abstract
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|
473 |
Design and Estimation of delay power and area for Parallel prefix adders - 2014 |
Abstract
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|
474 |
Design and FPGA implementation of compressor based Vedic multiplier - 2014 |
Abstract
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|
475 |
A Combined SDC SDF Architecture for Normal I/O Pipelined Radix-2 FFT - 2015 |
Abstract
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