ABSTRACT:

The project involves design of a straightforward RISC processor and simulating it. A Reduced Instruction Set compiler (RISC) is a microprocessor that had been designed to perform a little set of instructions, with the aim of skyrocketing the over all speed of the processor .The RISC concept initial originated in the early 1970’s when an IBM research team proved that twentyp.c of instruction did 80percent of the work .The RISC design follows the philosophy that one instruction should be performed each cycle

In this work, we have a tendency to analyze MIPS instruction format, instruction knowledge path, decoder module function and style theory based mostly on RISC (Reduced Instruction Set Computer) CPU instruction set. Furthermore, we design instruction fetch (IF) module of thirty two-bit CPU based mostly on RISC CPU instruction set. Function of IF module mainly includes fetch instruction and latch module, address arithmetic module, check validity of instruction module, synchronous management module. Operate of IF modules are implemented by pipeline and simulated successfully.

The plan of this project was to create a RISC processor as a building block in VHDL than later easily will be included in an exceedingly larger style. It can be helpful in systems where a drawback is straightforward to unravel in software but exhausting to unravel with control logic. However at a high level of complexity it is easier to implement the perform in software. In this project for simulation we have a tendency to use Modelsim for logical verification, and additional synthesizing it on Xilinx-ISE tool using target technology and performing putting & routing operation for system verification.