ABSTRACT:

Multiplication could be a advanced arithmetic operation, which is reflected in its comparatively high signal propagation delay, high power dissipation, and giant area demand. When choosing a multiplier for a digital system, the bitwidth of the multiplier is needed to be a minimum of as wide as the largest operand of the applications that are to be executed on that digital system. The bitwidth of the multiplier is, so, usually abundant larger than the info represented inside the operands, that results in unnecessarily high power dissipation and unnecessary long delay. This resource waste might partially be remedied by having several multipliers, every with a selected bitwidth, and use the particular multiplier with the tiniest bitwidth that's large enough to accommodate the current multiplication. Such a theme would assure that a multiplication would be computed on a multiplier that has been optimized in terms of power and delay for that specific bitwidth. However, using several multipliers with different bitwidths would not be an economical answer, mainly as a result of of the large area overhead.

We gift the dual-precision technique for integer multipliers. The twin-precision technique can cut back the ability dissipation by adapting a multiplier to the bitwidth of the operands being computed. The technique conjointly permits an increased computational throughput, by permitting many slender-width operations to be computed in parallel. We have a tendency to describe how to apply the twin-precision technique conjointly to signed multiplier schemes, like Baugh–Wooly and changed-Booth multipliers.

ADVANTAGES:

• A significant reduction in the power dissipation.
• Performing double-throughput multiplications.

APPLICATION:

• Baugh-Wooly Algorithm Implementation
• Modified Booth Algorithm Implementation
• LANGUAGE USED: VHDL

TOOLS REQUIRED:

• MODELSIM 6.5b-SE – Simulation
• XILINX-ISE 11.1i – Synthesis