ABSTRACT:

Double Data Rate (DDR) SDRAMs have been prevalent in the PC memory market lately and are widely used for networking systems. These memory devices are rapidly developing, with high density, high memory bandwidth and low device price. However, because of the high-speed interface technology and complex instruction-based mostly memory access control, a particular purpose memory controller is important for optimizing the memory access trade off. In this paper, a specific purpose DDR3 controller for prime-performance table lookup is proposed and a corresponding lookup circuit based mostly on the Hash-CAM approach is presented.

Content Addressable Memory (CAM) based techniques are widely employed in network equipment for quick table search.  However, in comparison to Random Access Memory (RAM) technology, CAM technology is restricted in terms of memory density, hardware price and power dissipation. CAM primarily based lookup circuit’s technology having higher performance, higher memory density and lower value.

In this paper, an advanced DDR3 memory controller design for top-performance table lookup is designed with a high performance Hash-CAM primarily based lockup circuit and its functionality is verified.

APPLICATION:

• Interface between CPU and DDR-SDRAM Processor
• Interface between PCI and DDR-SDRAM Processor
• High-Performance Network Processing

ADVANTAGES:

• Lower System cost
• Higher memory density
• Higher performance
• Improved Bandwidth

LANGUAGE USED:

• Verilog HDL

TOOLS REQUIRED:

• MODELSIM – Simulation.
• XILINX-ISE – Synthesis