ABSTRACTS:

The On-Chip bus is a vital system-on-chip (SoC) infrastructure that connects major hardware elements. Monitoring the on-chip bus signals is crucial to the SoC debugging and performance analysis/optimization. Unfortunately, such signals are difficult to look at since they're deeply embedded in a SoC and there are often no sufficient I/O pins to access these signals. Therefore, a simple approach is to embed a bus tracer in SoC to capture the bus signal trace and store the trace in an on-chip storage like the trace memory which might then be off loaded to outside world (the trace analyzer software) for analysis.

Unfortunately, the size of the bus trace grows rapidly. For example, to capture AMBA AHB 2.zero  bus signals running at two hundred MHz, the trace grows at two to 3 GB/s. Therefore, it's highly desirable to compress the trace on the fly so as to scale back the trace size. However, simply capturing / compressing bus signals isn't sufficient for SoC debugging and analysis, since the debugging / analysis desires are versatile: some designers would like all signals at cycle-level, while some others only care concerning the transactions. For the latter case, tracing all signals at cycle-level wastes a heap of trace memory. Thus, there must be a method to capture traces at totally different abstraction levels based on the specific debugging/analysis need.