A Look Ahead Clock Gating Based on Auto Gated Flip Flops - 2014
Clock gating is very helpful for reducing the facility consumed by digital systems. Three gating ways are known. The foremost fashionable is synthesis-based mostly, deriving clock enabling signals primarily based on the logic of the underlying system. It sadly leaves the majority of the clock pulses driving the flip-flops (FFs) redundant. A data-driven methodology stops most of these and yields higher power savings, however its implementation is complex and application dependent. A third technique called auto-gated FFs (AGFF) is easy however yields relatively small power savings. This project presents a novel methodology referred to as Look-Ahead Clock Gating (LACG), which combines all the three. LACG computes the clock enabling signals of every FF one cycle ahead of time, based mostly on this cycle knowledge of those FFs on which it depends. It avoids the tight timing constraints of AGFF and data-driven by allotting a full clock cycle for the computation of the enabling signals and their propagation. A closed-type model characterizing the facility saving per FF is presented. It is based on information-to-clock toggling possibilities, capacitance parameters and FFs' fan-in. The model implies a breakeven curve, dividing the FFs area into 2 regions of positive and negative gating come on investment. Whereas the bulk of the FFs fall within the positive region and hence ought to be gated, those falling in the negative region ought to not. Experimentation on industry-scale information showed 22.vi% reduction of the clock power, translated to 12.five% power reduction of the whole system.
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