A High Speed 256-Bit Carry Look Ahead Adder Design Using 22nm Strained Silicon Technology - 2015


During this project, a high speed 256-bit carry look ahead adder has been designed using 22nm strained silicon technology. The proposed adder combines the advantage of each the static and dynamic styles, which exhibits lower leakage, higher noise immunity and high speed. The speed performance of the proposed 256-bit adder is considerably improved by computing the even and therefore the odd carries separately by using 2 separate Manchester carry chains. The circuit is simulated in HSPICE within the high performance 22nm PTM strained silicon CMOS technology with a offer voltage of VDD = 0.8V. The simulation results show that the proposed 256bit adder implemented using 8-bit adder modules shows vital operating speed improvement compared to the traditional 256-bit adder based mostly on the quality four-bit MCC adder modules.

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