Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design


The previously proposed charge-sharing symmetric adiabatic logic (CSSAL) in an 8-bit S-box circuit is implemented during this paper using a multi-stage positive polarity Reed-Muller representation with a composite field technique. The CSSAL and alternative typical twin-rail adiabatic logics are evaluated from the read purpose of the transitional power fluctuation and the height current traces in the eight-bit S-box in order to compare their resistance against aspect-channel attacks. A technique to eliminate unwanted glitch current, the triple power clock supplies are applied to each inversion block; thus, the CSSAL S-box circuit performs uniform peak current traces and it's important power reduction, that is applicable for high security demand and low power devices, like sensible cards, radio frequency identity tags or wireless sensors. The results are obtained from the SPICE simulation with a zero.eighteen-μm one.8-V normal complementary metal-oxide semiconductor technology at an operating frequency band of one.25 KHz-seventy MHz.

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