Read and Write Voltage Signal Optimization for Multi-Level-Cell (MLC) NAND Flash Memory


The multi-level-cell (MLC) NAND flash channel exhibits nonstationary behavior over increasing program and erase (PE) cycles and information retention time. In this paper, an optimization theme for adjusting the read (quantized) and write (verify) voltage levels to adapt to the nonstationary flash channel is presented. Employing a model-primarily based approach to represent the flash channel, incorporating the programming noise, random telegraph noise (RTN), data retention noise and cell-to-cell interference as major signal degradation components, the write-voltage levels are optimized by minimizing the channel error likelihood. Moreover, for choosing the quantization levels for the read-voltage to facilitate soft LDPC decoding, an entropy-primarily based operate is introduced by that the voltage erasure regions (error dominating regions) are controlled to supply all-time low bit/frame error probability. The proposed write and browse voltage optimization schemes not solely minimize the error probability throughout the operational lifetime of flash memory, but also improve the decoding convergence speed. Finally, to attenuate the amount of read-voltage quantization levels whereas ensuring LDPC decoder convergence, the extrinsic info transfer (EXIT) analysis is performed over the MLC flash channel.

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