A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations

PROJECT TITLE :

A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations

ABSTRACT:

During this paper, we have a tendency to gift a brand new 9T SRAM cell that has sensible write ability and improves browse stability at the same time. Simulation results show that the proposed style increases scan static noise margin and ION/IOFF of scan path by 219% and 113%, respectively, at offer voltage of 300-mV over standard 6T SRAM cell in a very 90-nm CMOS technology. The proposed style lets us scale back the minimum operating voltage of SRAM (VDDmin) to 350 mV, whereas standard 6T SRAM cannot operate successfully with an acceptable failure rate at supply voltages below 725 mV. We tend to conjointly compared our design with 3 other SRAM cells from recent literature. To verify the proposed design, a 256-kb SRAM is intended using new 9T and typical 6T SRAM cells. Operating at their minimum possible VDDs, the proposed style decreases write and read power per operation by ninety two% and ninety threepercent, respectively, over the conventional rival. The realm of the proposed SRAM cell is increased by eighty threep.c over a typical 6T one. But, thanks to large ION/IOFF of scan path for 9T cell, we are able to place 1k cells in every column of 256-kb SRAM block, ensuing in the chance for sharing write and read circuitries of every column between more cells compared with typical 6T. So, the world overhead of 256kb SRAM primarily based on new 9T cell is reduced to thirty sevenp.c compared with 6T SRAM.

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