Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems - 2016

PROJECT TITLE :

Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems - 2016

ABSTRACT:

In resource-constrained embedded systems, on-chip cache memories play an necessary role in both performance and energy consumption. In distinction to browse operations, scant regard has been paid to optimizing write operations even though the energy consumed by write operations in the info cache constitutes a massive portion of the total energy consumption. Consequently, this paper proposes a write buffer-oriented (WO) cache architecture that reduces energy consumption within the L1 information cache. Observing that write operations are terribly doubtless to be merged in the write buffer because of their high localities, we construct the proposed WO cache design to utilize two schemes. Initial, the write operations update the write buffer however not the L1 knowledge cache, that is updated later by the write buffer once the write operations are merged. Write merging considerably reduces write accesses to the information cache and, consequently, energy consumption. Second, we more reduce energy consumption within the write buffer by filtering out unnecessary read accesses to the write buffer using a browse hit predictor. During this paper, we have a tendency to show that the proposed WO cache design is applicable to the traditional embedded processors that support both write-through and write-back policies. More, the experimental results verify that the proposed cache design reduces energy consumption in data caches up to fourteenp.c.

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