PROJECT TITLE :
During this paper, a high-frequency crosstalk compensation scheme for high speed multi-channel on-chip interconnect is proposed. Within the proposed scheme, a zero is inserted to the aggressor branch of the crosstalk feed-forward equalizer, that compensates for the high-frequency crosstalk, resulting in reduced timing jitter and increased eye opening. In order to verify the proposed scheme, an eight-channel ten-mm on-chip interconnect is implemented in one hundred thirty-nm CMOS method. Measurement results show that the proposed theme effectively removes the high frequency crosstalk and achieves a data rate of 2.nine Gb/s at a touch-error-rate below $10^-12$. The facility consumption of the proposed transceiver is regarding one mW which corresponds to an energy potency of 0.four pJ/bit.
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