Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges


Current industrial systems-on-chips (SoCs) designs integrate an increasingly massive range of predesigned cores and their variety is predicted to increase significantly within the near future. As an example, molecular-scale computing promises single or maybe multiple order-of-magnitude improvements in device densities. The network-on-chip (NoC) is an enabling technology for integration of enormous numbers of embedded cores on one die. The prevailing method of implementing a NoC with planar metal interconnects is deficient because of high latency and important power consumption arising out of long multi-hop links employed in knowledge exchange. The latency, power consumption and interconnect routing problems of conventional NoCs will be addressed by replacing or augmenting multi-hop wired ways with high-bandwidth single-hop long-vary wireless links. This reveal new opportunities for detailed investigations into the planning of wireless NoCs (WiNoCs) with on-chip antennas, suitable transceivers and routers. Moreover, as it is an emerging technology, the on-chip wireless links conjointly want to overcome significant challenges regarding reliable integration. In this paper, we tend to gift various challenges and rising solutions concerning the design of an economical and reliable WiNoC design.

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