PROJECT TITLE :
Capacitive-coupling-based mostly simultaneously bi-directional transceivers for chip-to-chip communication in three-dimensional integrated circuits are presented. By employing a 4-level signaling strategy with a completely unique cascaded capacitor configuration, the proposed transceivers can transmit and receive information simultaneously through one inter-chip coupling capacitor, and effectively improve the throughput per interconnect. In this work, the proposed cascaded capacitor structure and its signaling strategy are discussed in details and circuit solutions for transceivers are presented. A parasitic shielding technique is utilized within the electrode style to boost signal swings without area overheads. A $sixteen murm mtimes twenty murm m$ electrode provides the voltage margin as large as 195 mV at 1.a pair of V supply (verified by postlayout simulation) for signal sensing and recovery. The proposed transceivers are designed in a very industrial 65-nm complementary metal–oxide–semiconductor technology.
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