Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology


An innovative modular 3-D stacked multi-processor architecture is presented. The platform is composed of utterly identical stacked dies connected along by through-silicon-vias (TSVs). Every die features four thirty two-bit embedded processors and associated memory modules, interconnected by a three-D network-on-chip (NoC), which can route packets within the vertical direction. Superimposing identical planar dies minimizes design effort and manufacturing prices, guaranteeing at the identical time high flexibility and reconfigurability. A single die can be used either as a totally testable standalone chip multi-processor (CMP), or integrated in a very three-D stack, increasing the core count and consequently the system performance. To demonstrate the feasibility of this design, fully functional samples have been fabricated using a standard UMC ninety nm complementary metal–oxide–semiconductor process and stacked using an in-house, via-last Cu-TSV process. Initial results show that the proposed three-D-CMP is capable of operating at a target frequency of 400 MHz, supporting a vertical information bandwidth of three.a pair of Gb/s.

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