Reliability-aware simultaneous multithreaded architecture using online architectural vulnerability factor estimation


Miniaturisation in fashionable microprocessors increases susceptibility to soft errors leading to reliability degradation. Recently simultaneous multithreaded (SMT) architecture is utilised to boost fault tolerance. Despite full coverage, redundant checking in such schemes causes important performance and energy overheads. Fortunately, a number of the soft errors can be masked at the architectural level and architectural vulnerability issue (AVF) of a structure represents the portion of soft errors which result in a failure in the output of a program. In this study, the authors gift an infrastructure for on-line monitoring of AVF of sensitive structures of an SMT processor. Primarily based on estimated AVF, we tend to have introduced partial thread redundancy (PTR) protection scheme for intervals whose AVF is larger than a predefined threshold and the estimated AVF is used for adaptation between reliability improvement or performance enhancement, especially when the processor executes more than one workload. We have a tendency to have utilised SPEC CPU2006 benchmarks for AVF estimation of some necessary hardware resources such as issue queue, reorder buffer, load/store queue and register file. Experimental results show that the mean absolute error of our AVF estimation method varies from zero.04 to zero.07 and combined on-line AVF estimation and PTR protection, results in a reliability aware execution and lower performance overhead.

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