Asymmetric Dual-Spacer Trigate FinFET Device-Circuit Codesign and Its Variability Analysis


High- $k$ spacer materials are extensively studied these days for the enhancement of electrostatic control and suppression of short-channel effects in nanoscaled devices. However, the exorbitant increase in fringe capacitance due to high- $k$ spacers deteriorates the dynamic circuit performance. Interestingly, this paper demonstrates effective reduction in circuit delay with an optimum usage of high- $k$ spacer material. An asymmetric dual- $k$ spacer trigate (ADS-TG) FinFET architecture is employed for the purpose. From in depth three-D simulations, it's demonstrated that ADS-TG device significantly improves the general circuit delay and robustness performance whereas fully capturing the fringe capacitance effects. A FinFET inverter and a three-stage ring oscillator (RO3) are adopted to analyze the performances rigorously. As compared with the traditional device, the ADS-TG device hurries up the RO3 circuit by 22.half dozen% and 32.4% using high- $k$ spacer dielectrics HfO2 and TiO2, respectively. Contradictorily, a purely high- $k$ FinFET device deteriorates the RO3 delay per stage up to 11%. Furthermore, the results of provide voltage and underlap length on ADS-TG-based mostly RO3 delay over the conventional ones are also dealt in. The ADS-TG device and static RAM primarily based on this device convince be additional variation tolerant compared with the traditional configurations.

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