PROJECT TITLE :
Charged Board Model ESD Simulation for PCB Mounted MOS Transistors
During this paper, power MOS transistor behavior below charged board model (CBM) ESD impact is considered. The analysis of the MOSFET failure condition at the CBM ESD event is performed. The CBM equivalent circuit is proposed. The physical parameters of the PCB and device below check are replaced by the lumped RCL circuit. The MOSFET failure voltage calculation methodology is developed. This technique is based on the transient analysis of the CBM ESD equivalent circuit with the overall purpose open-source circuit simulator Qucs. This simplified method allows us to calculate CBM ESD voltage dangerous for the MOSFET with less than 20% error for a few application cases (pins while not ESD protection). CBM ESD tests are performed. Simulation and measurement results are in good match.
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