PROJECT TITLE :
Multi-standard high-throughput and low-power quasi-cyclic low density parity check decoder for worldwide interoperability for microwave access and wireless fidelity standards
This study presents a reconfigurable quasi-cyclic low density parity check (QC-LDPC) decoder for IEEE 802.16e worldwide interoperability for microwave access and IEEE 802.11n wireless fidelity communication standards. It supports multiple code-rates of 1/2, two/3, 3/4, five/6 and its architecture has been designed based mostly on column layered decoding technique to boost the convergence speed. The authors have instructed a register file based mostly approach to handle the shift property of the changed parity check matrix and a modified version of the matrix permutation technique has been introduced to reduce the amount of check nodes that handle multiple messages. Additionally, parallel processing has been incorporated in the decoder architecture to attain higher achievable throughput. This QC-LDPC decoder is implemented in ninety nm CMOS process and is post-layout simulated. It will achieve a throughput of 796 Mbps for a code-rate of five/6. With zero.nine V supply, it consumes 146 mW of total power at 149 MHz clock frequency.
Did you like this research project?
To get this research project Guidelines, Training and Code... Click Here