Analysis and Design of a Multi-Core Oscillator for Ultra-Low Phase Noise


In this paper, we tend to exploit an idea of coupling multiple oscillators to scale back phase noise (PN) to beyond the limit of what has been practically achievable thus way in a very bulk CMOS technology. We have a tendency to then apply it to demonstrate for the primary time an RF oscillator that meets the foremost stringent PN requirements of cellular basestation receivers whereas abiding by the method technology reliability rules. The oscillator is realized in digital sixty five-nm CMOS as a twin-core LC-tank oscillator based on a high-swing class-C topology. It's tunable at intervals four.07–four.91 GHz, while drawing thirty-nine–fifty nine mA from a two.15 V power supply. The measured PN is dBc/Hz and dBc/Hz at three MHz and 20 MHz offset, respectively, from a 4.07 GHz carrier, which makes it all-time low reported normalized PN of an integrated CMOS oscillator. Straightforward expressions for PN and interconnect resistance between the cores are derived and verified against circuit simulations and measurements. Analysis and simulations show that the interconnect resistance isn't essential even with a one% mismatch between the cores. This approach will be extended to a higher range of cores and achieve an arbitrary reduction in PN at the price of the power and area.

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