A 0.0054-mm2 Frequency-to-Current Conversion-Based Fractional Frequency Synthesizer in 32 nm Utilizing Deep Trench Capacitor PROJECT TITLE :A 0.0054-mm2 Frequency-to-Current Conversion-Based Fractional Frequency Synthesizer in 32 nm Utilizing Deep Trench CapacitorABSTRACT:In this transient, a frequency-to-current conversion-primarily based fractional frequency synthesizer is implemented in 32-nm technology utilizing a high-density deep trench capacitor. The technique proposed here will replace the use of multiple crystal oscillators or a phase-locked loop for medium accuracy clock generation with terribly low chip area and power consumption. Additionally to exploiting the inherently low variation of capacitors as compared to that of transistors, the proposed circuit generates an output frequency proportional to the capacitor ratio, canceling out any little method-voltage-temperature (PVT) dependences of the capacitor. The performance of the fractional synthesizer is verified from chip measurement results. An output frequency vary of sixteen–156 MHz is roofed with a frequency resolution of 0.8 MHz using a 4-MHz reference clock. The whole space of the frequency synthesizer core is only 0.0054 mm2, and it consumes 116 $mumboxW$ of power from a 0.9-V supply while generating an output frequency of forty eight MHz. The output frequency variation is ±zero.14% at forty eight MHz for a temperature sweep from −40 °C to 90 °C. Periodic jitter measured from an on-chip high-resolution jitter measurement circuit is a hundred and fifteen ps (rms) at seventy six MHz. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Analysis and Design of a Multi-Core Oscillator for Ultra-Low Phase Noise Tradeoffs Between Transmission Intervals and Delays for Decentralized Networked Control Systems Based on a Gain Assignment Approach