Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core


As thread level parallelism in applications has continued to expand, so has research in chip multi-core processors. As additional and a lot of applications become multi-threaded we tend to expect to search out a growing range of threads executing on a machine. As a consequence, the operating system can require increasingly larger amounts of CPU time to schedule these threads efficiently. Rather than perpetuating the trend of performing a lot of advanced thread scheduling within the operating system, we tend to propose a scheduling mechanism that may be efficiently implemented in hardware additionally. Our approach of identifying multi-threaded application bottlenecks such as thread synchronization sections enhances the Fairness-aware Scheduler method. It achieves a mean speed from 11.five % (geometric mean) compared to the state-of-the-art Fairness-aware Scheduler.

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