PROJECT TITLE :
A High-Level Power Model for MPSoC on FPGA
This paper presents a framework for top-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is predicated on abstract execution profiles, referred to as event signatures. Thence, it is capable of achieving good evaluation performance, thereby making the technique highly helpful in the context of early system-level design house exploration. We tend to have integrated the power estimation technique in a system-level MPSoC synthesis framework. Using this framework, we tend to have designed a vary of different candidate MPSoC architectures and compared our power estimation results to those from real measurements on a Virtex-half-dozen FPGA board.
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