Obfuscating DSP Circuits via High-Level Transformations - 2015
This project presents a completely unique approach to design obfuscated circuits for digital signal processing (DSP) applications using high-level transformations, a key-primarily based obfuscating finite-state machine (FSM), and a reconfigurator. The goal is to style DSP circuits that are more durable to reverse engineer. High-level transformations of iterative data-flow graphs have been exploited for area-speed-power tradeoffs. This is the first try to develop a style flow to use high-level transformations that not only meet these tradeoffs however conjointly simultaneously obfuscate the architectures each structurally and functionally. Several modes of operations are introduced for obfuscation where the outputs are meaningful from an indication processing purpose of view, however are functionally incorrect. Examples of such modes embody a 3rd-order digital filter that may conjointly implement a sixth-order or ninth-order filter in a time-multiplexed manner. The latter 2 modes are meaningful but represent functionally incorrect modes. Multiple meaningful modes will be exploited to reconfigure the filter order for various applications. Different modes might correspond to nonmeaningful modes. A correct key input to an FSM activates a reconfigurator. The configure data controls various modes of the circuit operation. Useful obfuscation is accomplished by requiring use of the proper initialization key, and configure knowledge. Wrong initialization key fails to enable the reconfigurator, and a wrong configure information activates either a meaningful however nonfunctional or nonmeaningful mode. Chance of activating the correct mode is significantly reduced resulting in an obfuscated DSP circuit. Structural obfuscation is additionally achieved by the proposed methodology via high-level transformations. Experimental results show that the overhead of the proposed methodology is little, while a robust obfuscation is attained. For example, the world overhead for a (31)th-order IIR filter benchmark is only 17.seven% with a 128-bit configuration key, where one = l = 8, i.e., the order of this filter ought to be a multiple of three, and will vary from three to twenty four.
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