Testing of Copper Pillar Bumps for Wafer Sort PROJECT TITLE :Testing of Copper Pillar Bumps for Wafer SortABSTRACT: Employing a copper pillar interconnect in flip chip packaging provides a lead-free resolution that is additional reliable, and also scalable to very fine pitch. Vertical probe card technology, conjointly known as buckling beam technology, was employed in characterization of wafer probe method and electrical contact on solder bumps and copper pillars at 150 $murm m$ pitch arrays. Probe contact was investigated by modeling the scrub, penetration or deformation on a bump under various conditions of wafer probe and experimentally tested on wafers on copper pillars, solder bumps of different metallurgies or sheet wafers. One-probe contact check system was devised to study the contact behavior of an enquiry on a bump. Varied probe tip geometries including wedge, pointed and flat, were studied. Probing procedures were investigated for achieving reliable electrical contact for massive pitch area array bumps furthermore fine pitch, 50 $murm m$, copper pillar array bumps using 2 totally different wafer check technologies. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Development of Wafer-Level Warpage and Stress Modeling Methodology and Its Application in Process Optimization for TSV Wafers Time-Domain Green's Function-Based Parametric Sensitivity Analysis of Multiconductor Transmission Lines
