Development of Wafer-Level Warpage and Stress Modeling Methodology and Its Application in Process Optimization for TSV Wafers

PROJECT TITLE :

Development of Wafer-Level Warpage and Stress Modeling Methodology and Its Application in Process Optimization for TSV Wafers

ABSTRACT:

Through-silicon via (TSV) technology has been widely investigated recently for 3-D electronic packaging integration. Reducing TSV wafer warpage is one among the most difficult issues for successfully subsequent processes. During this paper, a wafer-level warpage modeling methodology has been developed by the finite part analysis technique using a similar material model. The developed modeling methodology has been verified by numerical results and experimental data. Using the developed model, wafer warpage has been simulated and analyzed by considering different factors, such as annealing temperature, copper (Cu) overburden thickness, TSV depth, and diameter. Simulation results show that wafer warpage will increase with increasing annealing temperature and Cu overburden thickness. Such findings have been successfully utilized in TSV process optimization to cut back wafer warpage after annealing method. A world-native modeling methodology has also been implemented to work out wafer stress accurately. Wafer bending stress is high at wafer surface and shut to TSV edge. Wafer bending stress increases with increasing TSV diameter and it's higher at the edge of TSVs with finer pitch.

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