PROJECT TITLE :

Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization

ABSTRACT:

This brief presents a tool for optimizing the energy and delay (E/D) of static RAM designs to fulfill a selected die yield constraint. This permits the tool to account for the consequences of process variation and to trade off yield with performance and energy. To accomplish this, we tend to use a combination of simulation and modeling techniques to determine the minimum wordline (WL) pulsewidth required for each the read and write operations to satisfy a user-specified die yield. The use of a hierarchical model permits us to calculate the E/D of a full macro that is margined to fulfill a specific die yield. By sweeping across the doable design house, we are able to spot Pareto optimal designs. The tool structure described in this brief permits comparison across totally different array topologies, process technologies, and circuit decisions as well as assist methods. Using this tool, we tend to realize that adding a WL boosting scheme results in an overall energy savings, despite the overhead of using a charge pump circuit, due to an improved scan delay distribution.