PROJECT TITLE :

Variation-Tolerant Sensing Circuit for Spin-Transfer Torque MRAM

ABSTRACT:

A sensing circuit is described for a spin-transfer torque magnetic random access memory (STT-MRAM). The sensitivity to the variations of magnetic tunneling junction (MTJ) resistance and transistor parameters is reduced by using the degenerated cross-coupled sensing circuit (DCCSC). The reference cell is also implemented to attenuate the variation sensitivity and avoid any read disturbance. The proposed DCCSC and therefore the reference cell are applied to a sixty four-kb STT-MRAM array. Simulation results with a 65-nm CMOS process parameter show that the sensing margin is larger than five hundred mV, for both the parallel and antiparallel states, and also the access time is a pair of ns, and the energy per bit sensing is solely 0.195 pJ, assuming that the variation of the MTJ resistance is +/−20% and tunneling magnetoresistance ratio is one hundred%.