PROJECT TITLE :

Energy-efficient capacitor-splitting DAC scheme with high accuracy for SAR ADCs

ABSTRACT:

An energy-efficient capacitor-splitting digital-to-analogue converter (DAC) scheme with high-accuracy for successive approximation register (SAR) analogue-to-digital converters (ADCs) is presented. The proposed methodology uses a split-capacitive-array DAC structure and optimises the switching energy throughout conversion using energy-economical 'up' transition. The proposed switching theme achieves a ninety six.ninety onepercent switching energy reduction and a seventy fivep.c space reduction compared with the traditional methodology. In addition, the third reference voltage (Vcm) has no effect on the accuracy of the SAR ADC except the least significant bit, resulting in a smart trade-off between the energy-potency and accuracy of the ADC.