PROJECT TITLE :

A Multibit Delta–Sigma Modulator With Double Noise-Shaped Segmentation

ABSTRACT:

This temporary proposes an occasional-power design for a discrete-time (DT) delta–sigma modulator to require full blessings of increased quantization levels. Within the proposed architecture, noise-shaped segmentation is applied to each the quantizer and therefore the feedback digital-to-analog converter to take care of a high resolution and a high linearity and, at the identical time, keep the hardware complexity low. This leads to a significantly reduced output swing of the integrator to attenuate the slewing-connected distortion in a DT implementation. The ensuing uniform linear settling behavior will tolerate a relatively massive settling error without degrading the performance, which greatly relaxes the bandwidth demand of the op-amp design. The reduced output swing conjointly allows the utilization of low-gain amplifiers, that is notably enticing for a complicated technology in that the intrinsic gain of the transistor is degraded. The proposed design is analyzed and verified through simulation.