PROJECT TITLE :

Simulation-Based Method for Synthesizing Soft Error Tolerant Combinational Circuits

ABSTRACT:

Due to current technology scaling trends, digital styles are changing into a lot of sensitive to radiation-induced particle hits ensuing from radioactivity decay and cosmic rays. An occasional-energy particle can flip the output of a gate, ensuing in an exceedingly soft error if it propagates to a circuit output. Therefore, soft error tolerance has become an necessary criterion in digital system design. During this work, we have a tendency to propose a simulation-based approach to reduce the soft error probability of circuit failure in combinational logic circuits. The proposed methodology is based on maximizing the likelihood of logical masking when a soft error happens. This maximization is completed by extracting sub-circuits from a creative multi-level circuit, and then re-synthesizing each extracted sub-circuit to increase fault masking against one fault. We have a tendency to gift a two-level synthesis theme to maximize soft error masking on every extracted sub-circuit. This scheme provides a heuristic that finds the best set of cubes to cover the input patterns of an extracted sub-circuit. A Fast Extraction (FX) algorithm is used to enhance the area overhead of synthesized two-level sub-circuits. Experimental results on some MCNC combinational benchmarks show that, on average, a likelihood of circuit failure reduction of 32p.c is achieved compared to the initial circuit. The average area overhead is 40% of the initial circuit.