PROJECT TITLE :

A Low-Power CMOS Image Sensor With Area-Efficient 14-bit Two-Step SA ADCs Using Pseudomultiple Sampling Method

ABSTRACT:

This brief presents a coffee-power CMOS image sensor with fourteen-bit column-parallel two-step (TS) successive approximation (SA) analog-to-digital converters (ADCs). The proposed TS SA ADC adopts a pseudomultiple sampling method to scale back the facility consumption and the world. For implementing the 14-bit ADC, it only uses a capacitor digital-to-analog converter of half dozen bits instead of 14 bits. The multiple sampling conjointly suppresses the noise of a pixel and a column-parallel ADC. The image sensor is fabricated by using the zero.13-μm CMOS method. The measurement results show that the temporal noise is 82.seven μVrms, and the power consumption is fifty five.one μW for one column ADC with a programmable gain amplifier. With the digital correlated double sampling and therefore the TS calibration method, the proposed ADC achieves the column mounted-pattern noise of zero.ninety eight LSB and a differential nonlinearity of +0.ninety nine/-0.ninety LSB.