Majority-Inverter Graph: A New Paradigm for Logic Optimization

PROJECT TITLE :

Majority-Inverter Graph: A New Paradigm for Logic Optimization

ABSTRACT:

In this paper, we tend to propose a paradigm shift in representing and optimizing logic by using solely majority (MAJ) and inversion (INV) functions as basic operations. We have a tendency to represent logic functions by majority-inverter graph (MIG): a directed acyclic graph consisting of three-input majority nodes and regular/complemented edges. We tend to optimize MIGs via a new Boolean algebra, based mostly solely on majority and inversion operations, that we tend to formally axiomatize in this paper. As a complement to MIG algebraic optimization, we tend to develop powerful Boolean methods exploiting global properties of MIGs, such as bit-error masking. MIG algebraic and Boolean methods together attain terribly high optimization quality. Considering the set of IWLS’05 benchmarks, our MIG optimizer (MIGhty) enables a 7% depth reduction in LUT-half-dozen circuits mapped by ABC while also reducing size and power activity, with respect to similar and-inverter graph (AIG) optimization. Focusing on arithmetic intensive benchmarks instead, MIGhty allows a 16% depth reduction in LUT-six circuits mapped by ABC, once more with respect to similar AIG optimization. Employed as front-finish to a delay-vital twenty two-nm application-specified integrated circuit flow (logic synthesis + physical design) MIGhty reduces the typical delay/space/power by 13%/four%/three%, respectively, over 31 educational and industrial benchmarks. We tend to conjointly demonstrate delay/area/power improvements by 10%/ten%/five% for a business FPGA flow.

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