PROJECT TITLE :
High-Throughput LDPC Decoder on Low-Power Embedded Processors
Real-time economical implementations of LDPC decoders have long been considered solely reachable using dedicated hardware architectures. Attempts to implement LDPC decoders on CPU and GPU devices have result in high power consumptions along with high processing latencies that are incompatible with most embedded and mobile transmission systems. In this letter, we tend to propose ARM-primarily based decoders that go from fifty to a hundred Mbps whereas executing ten layered-decoding iterations. We hereby demonstrate that economical LDPC decoders can be implemented on a coffee-power programmable design. The proposed decoders are competitive with recent GPU related works. Thus, software LDPC decoders constitute a response to software outlined radio constraints.
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