PROJECT TITLE :
Efficient and Correct by Construction Assertion-Based Synthesis
We propose a unifying formalization of the ideas of monitor and reactant, and derive a modular synthesis technique to achieve automatic generation of compliant modules from declarative temporal specifications. The founding dependence relation and its hardware interpretation give an algorithm to automatically decide that signals are observed and that are generated. The strategy is economical, and it synthesizes management circuits during a few seconds. The results obtained on classical benchmarks show that our technique compiles properties a lot of efficiently than previous prototype tools.
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