Substrate-Voltage Modulation of Currents in Symmetric SOI Lateral Bipolar Transistors


The modulation of the currents during a symmetric Semiconductor-on-Insulator (SOI) lateral bipolar transistor with a voltage applied to the SOI substrate is studied. For an n-p-n transistor, a positive substrate bias may greatly increase the collector current, particularly at low values, while having relatively little effect on the base current. Similarly, a negative substrate bias may greatly increase the collector current of a p-n-p transistor. The physical mechanisms accountable for the modulation effects are discussed. The potential of using substrate bias to boost the performance of symmetric SOI lateral bipolar circuits is briefly mentioned.

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