New Approach to the Reduction of Sign-Extension Overhead for Efficient Implementation of Multiple Constant Multiplications


Sign-extension of operands within the shift-add network of multiple constant multiplication (MCM) leads to a vital overhead in terms of hardware complexity along with computation time. This paper presents an efficient approach to minimize that overhead. Within the proposed method, the shift-add network of an MCM block is partitioned into three types of sub-networks based on the varieties of fundamentals and interconnections they involve. For every type of sub-network, a theme that takes the most effective advantage of the redundancy in the computation of sign-extension half is proposed to attenuate the overhead. Moreover, we have a tendency to also propose a way to avoid the additions regarding the most vital bits (MSBs) of the fundamentals. Experimental results show that the proposed methodology invariably ends up in implementations of MCM blocks with very cheap vital path delay. The prevailing ways for the minimization of sign-extension overhead are designed particularly for single multiplication or MCM blocks of FIR filter, but the proposed method will be used to cut back the overhead of sign-extension for MCM blocks of any application. Within the case of FIR filters, the proposed methodology outperforms alternative competing strategies in terms of essential path delay, area-delay product (ADP), and power-delay product (PDP), yet.

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