Methods to Enhance the Performance of InGaAs/InP Heterojunction Tunnel FETs


This paper presents a simulation study of In0.53Ga0.47As/InP heterojunction gate-overlapped-source tunnel FETs (GoS-TFETs) with pocket counter-doping. The result of channel quantization on the line tunneling is taken into account within the semiclassical simulations employing a new model that modifies the band edge within the inversion layer. The little bandgap of the source material In0.53Ga0.47As leads to an improved tunnel rate, whereas the wide bandgap of the channel/drain material InP reduces ambipolar leakage. The simulations show that, for the case of perfectly aligned p-n-junction and heterojunction, the type-I band alignment and the big band offsets delay suppress lateral (point) tunneling relative to vertical (line) tunneling that improves the subthreshold swing (SS). The counter-doped pocket in the source region advances the onset of line tunneling relative to purpose tunneling that conjointly assists in mitigating the results of purpose tunneling. In this method, each large band offset and counter-doped pocket improve the subthreshold behavior of the TFET. Putting the p-n-junction inside the InP region makes the vertical tunneling even more dominant and, thus, reduces the SS. The suggested modifications might be useful to improve the device performance beyond that of the standard GoS-TFETs.

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