High-Throughput Multi-Core LDPC Decoders Based on x86 Processor


Low-Density Parity-Check (LDPC) codes are an economical means to correct transmission errors in digital Communication systems. Although initially targeting strictly to ASICs thanks to computation complexity, LDPC decoders are recently ported to multicore and several-core systems. Most works focused on making the most of GPU devices. In this paper, we propose an alternate resolution primarily based on a layered OMS/NMS LDPC decoding algorithm which will be efficiently implemented on a multi-core device using Single Instruction Multiple Information (SIMD) and Single Program Multiple Information (SPMD) programming models. Many experimentations were performed on a x86 processor target. Throughputs up to a hundred and seventy Mbps were achieved on a single core of an INTEL Core i7 processor when executing 20 layered-based decoding iterations. Throughputs reaches up to 560 Mbps on four INTEL Core-i7 cores. Experimentation results show that the proposed implementations achieved similar BER correction performance than previous works. Moreover, much higher throughputs have been achieved by comparison with all previous GPU and CPU works. They range from x1.4 to x8 by comparison with recent GPU works.

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